1. Field of the Invention
The present invention relates generally to semiconductor structures and manufacturing. More particularly, the present invention relates to the formation of metal-insulator-metal capacitors.
2. Related Art
Advances in semiconductor manufacturing technology have led to the integration of millions of circuit elements, such as transistors, on a single integrated circuit (IC). In order to integrate increasing numbers of circuit elements onto an IC it has been necessary to reduce the dimensions of the various component parts. Not only have interconnect line widths become smaller, but so have the dimensions of metal-oxide-semiconductor field effect transistors and other integrated devices, such as capacitors.
Metal-electrode capacitors are widely used in mixed-signal/radio frequency (RF) ICs for better linearity and higher Q (quality factor) (due to lower electrode resistance). MIM (metal-insulator-metal) capacitors have been commercially available in the standard CMOS (complimentary metal oxide silicon) mixed-signal process with aluminum interconnect, by adding steps to the process flow. However, similar MIM capacitors are being developed for the most advanced copper interconnects, which is replacing the aluminum interconnects in the 0.15 xcexcm (micrometer=10xe2x88x926) generation and beyond. Due to the uniqueness in the copper damascene process, there is no simple/low-cost way of making MIM capacitors.
What is desired is a method of making copper MIM capacitors using fully compatible CMOS logic process techniques.
The capacitors made according to the present invention are specially designed for the copper dual-damascene process. These capacitors are fully CMOS logic process compatible. There are no extra process steps required and hence no extra cost.
The invention comprises forming a first copper or copper alloy metal layer in a first dielectric layer over a substrate. An etch stop layer and a second dielectric layer are formed on the first dielectric layer and first metal layer.
A patterned masking layer (known as the via photo resist layer) is formed over the second dielectric layer. The exposed portion of the second dielectric layer is removed, so that a first opening (say, for the capacitor) and a second opening (say, for the via) are formed in the second dielectric layer, thereby exposing portions of the stop layer above a first region and a second region of the first metal layer, respectively.
Another patterned masking layer (known as the metal photo resist layer) is formed such that a further portion of the second dielectric layer and a portion of the stop layer are exposed. The exposed portions of the second dielectric layer and the stop layer are removed, thereby exposing a portion of the second region of the first metal layer. The first and the second openings are filled with a copper or copper alloy thereby forming a second metal layer, wherein a MIM capacitor is formed by the first region of the first metal layer, the stop layer and the filled first opening, and the filled second opening forms a via between the first and second metal layers.
In the advanced CMOS process, there are typically several metal layers. By repeating the above process for multiple layers, a stacked MIM capacitance can form to achieve high density (that is, with high capacitance per unit area.)
These and other objects, advantages and features will become readily apparent in view of the following detailed description of the invention.